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Routing Signal Nets in VLSI Design
Sarnath Ramnath
Tuesday, October 19, 2003 at 3:30pm in Olin 320
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An important problem in VLSI design is that of routing wires that
carry the signals from outputs of the gate (source) to the inputs of
the following gates (sinks). In the EDA (Electronic Design Automation)
community, this is known as the problem of routing signal nets.
I will talk about mathematical models for delay, contraints placed on the
route, and some recent results of mine that established the first provably
good approximation algorithm for routing in the presence of obstacles.
Refreshments will be served.
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Sarnath Ramnath is currently Professor and Chair of the Department
of Computer Science at Minnesota State University, St Cloud.
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For the MCS seminar schedule see
http://www.gac.edu/oncampus/academics/mcs/mcs-seminar/
If you or someone you know is interested in giving a talk this year,
contact David Wolfe at wolfe@gustavus.edu or San Skulrattanakulchai at
sskulrat@gustavus.edu.
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